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NCP1392B High-Voltage Half-Bridge Driver with Inbuilt Oscillator
The NCP1392B is a self-oscillating high voltage MOSFET driver primarily tailored for the applications using half bridge topology. Due to its proprietary high-voltage technology, the driver accepts bulk voltages up to 600 V. Operating frequency of the driver can be adjusted from 25 kHz to 250 kHz using a single resistor. Adjustable Brown-out protection assures correct bulk voltage operating range. An internal 100 ms PFC delay timer guarantee that the main downstream converter will be turned on in the time the bulk voltage is fully stabilized. The device provides fixed dead time which helps lowering the shoot-through current.
Features http://onsemi.com MARKING DIAGRAMS
8 1 SOIC-8 CASE 751 8 1392B ALYWW G
1
* * * * * * * * * * * * * * * * * *
Wide Operating Frequency Range - from 25 kHz to 250 kHz Minimum frequency adjust accuracy $3% Fixed Dead Time - 0.6 ms Adjustable Brown-out Protection for a Simple PFC Association 100 ms PFC Delay Timer Non-latched Enable Input Internal 16 V VCC Clamp Low Startup Current of 50 mA 1 A / 0.5 A Peak Current Sink / Source Drive Capability Operation up to 600 V Bulk Voltage Internal Temperature Shutdown SOIC-8 or PDIP-8 Package These are Pb-Free Devices Flat Panel Display Power Converters Low Cost Resonant SMPS High Power AC/DC Adapters for Notebooks Offline Battery Chargers Lamp Ballasts
A L Y WW G
= Assembly Location = Wafer Lot = Year = Work Week = Pb-Free Package
PINOUT
VCC Rt BO GND Vboot Mupper HB Mlower
Typical Applications ORDERING INFORMATION
Device NCP1392BDR2G Package SOIC-8 (Pb-Free) Shipping 2500 / Tape & Reel
For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D.
(c) Semiconductor Components Industries, LLC, 2008
October, 2008 - Rev. 1
1
Publication Order Number: NCP1392/D
NCP1392B
Rbo1 Dboot Cboot M1 + DC OUTPUT
VCC AC OUTPUT PFC FRONT STAGE + Cbulk Rt Bo GND Rbo2 Rf Rfmax Rfstart
Vboot Mupper HB Mlower M2
NCP1392
CSS
Figure 1. Typical Application Example
PIN FUNCTION DESCRIPTION
Pin # 1 2 3 Pin Name VCC Rt BO Function Supplies the Driver Timing Resistor Brown-Out Pin Description The driver accepts up to 16 V (given by internal zener clamp) Connecting a resistor between this pin and GND, sets the operating frequency Detects low input voltage conditions. When brought above Vref_EN, it stops the driver. Operation is restored (without any delay) when BO pin voltage drops 100 mV below Vref_EN.
4 5 6 7 8
GND Mlower HB Mupper Vboot
IC Ground Low-Side Driver Output Half-Bridge Connection High-Side Driver Output Bootstrap Pin Drives the lower side MOSFET Connects to the half-bridge output Drives the higher side MOSFET The floating supply terminal for the upper stage
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NCP1392B
VDD
Vboot
S D Vref Ct + -
Q
Pulse Trigger
Level Shifter
S R
Q Mupper Q
+ -
Vref
CLK R Q Bridge UV Detect
Rt
IDT
PFC Delay (100ms)
VCC
VCC
VDD
Vref PON RESET VCC Management Mlower DELAY
VCC
VCC Clamp TSD
- +
+ - VrefEN
0.5ms Filter
BO
+ -
+ - VrefBO
20ms Filter
SW
Ihyster
HIGH Level for 50ms After VCC On GND
Figure 2. Internal Circuit Architecture
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MAXIMUM RATINGS TABLE
Symbol Vbridge Vboot - Vbridge VDRV_HI VDRV_LO High Voltage Bridge Pin - Pin 6 Floating Supply Voltage High-Side Output Voltage Low-Side Output Voltage Rating Value -1 to +600 0 to 20 Vbridge - 0.3 to Vboot + 0.3 -0.3 to VCC +0.3 $50 20 -0.3 to 5 -0.3 to 10 mm2 Cooper 35 mm Cooper 35 mm 178 147 -60 to +150 2 200 Unit V V V V V/ns mA V V C/W C/W C kV V
dVbridge/dt Allowable Output Slew Rate ICC V_Rt Maximum Current that Can Flow into VCC Pin (Pin 1), (Note 1) Rt Pin Voltage Maximum Voltage, All Pins (Except Pins 4 and 5) RqJA RqJA Thermal Resistance Junction-to-Air, IC Soldered on 50
Thermal Resistance Junction-to-Air, IC Soldered on 200 Storage Temperature Range
mm2
ESD Capability, Human Body Model (All Pins Except Pins 1 , 6, 7 and 8) ESD Capability, Machine Model (All Pins Except Pins 1, 6, 7 and 8)
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect device reliability. 1. This device contains internal zener clamp connected between VCC and GND terminals. Current flowing into the VCC pin has to be limited by an external resistor when device is supplied from supply which voltage is higher than VCCclamp (16 V typically). The ICC parameter is specified for VBO = 0 V.
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VCC = 12 V, unless otherwise noted)
ELECTRICAL CHARACTERISTICS (For typical values TJ = 25C, for min/max values TJ = -40C to +125C, Max TJ = 150C,
Characteristic SUPPLY SECTION Pin 1 1 1 1 1 1 1 1 1 1 Symbol VCCON VCCmin VbootON Vbootmin VCCreset ICC ICC ICC1 ICC2 ICC3 ICC4 ICC4 8 8 8 1 2 2 2 2 5, 7 Iboot1 Iboot2 Iboot3 VCCclamp FSW min FSW max Vref RT Rtdischarge DC Min 10 8 7.8 7 - - - - - - - - - - - 15.4 24.25 208 3.33 - 48 Typ 11 9 8.8 8 6.5 - - 2.2 3.4 2.56 - - 0.3 1.44 0.1 16 25 245 3.5 500 50 Max 12 10 9.8 9 - 50 65 - - - 400 470 - - - 17.5 25.75 282 3.67 - 52 Unit V V V V V mA mA mA mA mA mA mA mA mA mA V kHz kHz V W %
Turn-On Threshold Level, VCC Going Up Minimum Operating Voltage after Turn-On Startup Voltage on the Floating Section Cutoff Voltage on the Floating Section, VCC Level at which the Internal Logic gets Reset Startup Current, VCC < VCCON, 0C v Tamb v +125C Startup Current, VCC < VCCON, -40C v Tamb < 0C Internal IC Consumption, No Output Load on Pins 8/7 - 5/4, Fsw = 100 kHz Internal IC Consumption, 1 nF Output Load on Pins 8/7 - 5/4, Fsw = 100 kHz Consumption in Fault Mode (Drivers Disabled, VCC > VCC(min), RT = 3.5 kW) Consumption During PFC Delay Period, 0C v Tamb v +125C Consumption During PFC Delay Period, -40C v Tamb < 0C Internal IC Consumption, No Output Load on Pin 8/7 FSW = 100 kHz Internal IC Consumption, 1 nF Load on Pin 8/7 FSW = 100 kHz Consumption in Fault Mode (Drivers Disabled, Vboot > Vbootmin) VCC Zener Clamp Voltage @ 20 mA INTERNAL OSCILLATOR Minimum Switching Frequency, Rt = 35 kW on Pin 2, DT = 600 ns Maximum Switching Frequency, Rt = 3.5 kW on Pin 2, DT = 600 ns Reference Voltage for all Current Generations Internal Resistance Discharging Csoft-start Operating Duty Cycle Symmetry NOTE: Maximum capacitance directly connected to Pin 2 must be under 100 pF. DRIVE OUTPUT Output Voltage Rise Time @ CL = 1 nF, 10-90% of Output Signal Output Voltage Fall Time @ CL = 1 nF, 10-90% of Output Signal Source Resistance Sink Resistance Deadtime Leakage Current on High Voltage Pins to GND (600 Vdc) PROTECTION Brown-Out Input Bias Current Brown-Out Level Hysteresis Current, Vpin3 < VBO Reference Voltage for EN Input Enable Comparator Hysteresis Propagation Delay Before Drivers are Stopped Delay Before Any Driver Restart Temperature Shutdown Hysteresis
5, 7 5, 7 5, 7 5, 7 5,7 6,7,8 3 3 3 3 3 3 - - -
Tr Tf ROH ROL Tdead IHVLeak IBObias VBO IBO Vref EN EN_Hyste EN_Delay PFC Delay TSD TSDhyste
- - - - 540 - - 0.95 15.6 1.9 - - - 140 -
40 20 12 5 610 - 0.01 1 18.2 2 100 0.5 100 - 30
- - - - 720 5 - 1.05 20.7 2.1 - - - - -
ns ns W W ns mA mA V mA V mV ms ms C C
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11.01 11.00 10.99 VOLTAGE (V) VOLTAGE (V) -20 0 20 40 60 80 100 120 10.98 10.97 10.96 10.95 10.94 10.93 10.92 10.91 -40 8.98 8.97 8.96 8.95 8.94 8.93 8.92 8.91 8.90 -40 -20 0 20 40 60 80 100 120
TEMPERATURE (C)
TEMPERATURE (C)
Figure 3. VCCon
8.85 8.80 VOLTAGE (V) 8.75 8.70 8.65 8.60 8.55 -40 8.10 8.05 8.00 7.95 7.90 7.85 7.80 -20 0 20 40 60 80 100 120 7.75 -40 -20 0
Figure 4. VCCmin
VOLTAGE (V)
20
40
60
80
100
120
TEMPERATURE (C)
TEMPERATURE (C)
Figure 5. VBOOTon
Figure 6. VBOOTmin
20 18 16 RESISTANCE (W) RESISTANCE (W) -20 0 20 40 60 80 100 120 14 12 10 8 6 4 2 0 -40
8 7 6 5 4 3 2 1 0 -40 -20 0 20 40 60 80 100 120
TEMPERATURE (C)
TEMPERATURE (C)
Figure 7. ROH
Figure 8. ROL
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243.4 243.2 FREQUENCY (kHz) FREQUENCY (kHz) -20 0 20 40 60 80 100 120 243.0 242.8 242.6 242.4 242.2 242.0 241.8 -40 25.05 25.00 24.95 24.90 24.85 24.80 24.75 -40
-20
0
20
40
60
80
100
120
TEMPERATURE (C)
TEMPERATURE (C)
Figure 9. FSWmax
45.0 40.0 35.0 CURRENT (mA) CURRENT (mA) 30.0 25.0 20.0 15.0 10.0 5.0 0.0 -40 -20 0 20 40 60 80 100 120 450 400 350 300 250 200 150 100 50 0 -40 -20 0
Figure 10. FSWmin
20
40
60
80
100
120
TEMPERATURE (C)
TEMPERATURE (C)
Figure 11. ICC_startup
Figure 12. ICC4
580 560 540 RESISTANCE (W) 520 TIME (ns) -20 0 20 40 60 80 100 120 500 480 460 440 420 400 -40
645 640 635 630 625 620 615 610 -40 -20 0 20 40 60 80 100 120
TEMPERATURE (C)
TEMPERATURE (C)
Figure 13. Rt_discharge
Figure 14. Tdead
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109 108 107 105 104 103 102 101 100 90 -40 -20 0 20 40 60 80 100 120 VOLTAGE (V) 106 TIME (ms) 2.008 2.006 2.004 2.002 2.000 1.998 1.996 1.994 1.992 1.990 -40 -20 0 20 40 60 80 100 120
TEMPERATURE (C)
TEMPERATURE (C)
Figure 15. PFCdelay
Figure 16. Vref_EN
1.015 1.014 1.013 VOLTAGE (V) 1.012 1.011 1.010 1.009 1.008 1.007 -40 -20 0 20 40 60 80 100 120 VOLTAGE (mV)
110 108 106 104 102 100 98 96 94 92 90 -40 -20 0 20 40 60 80 100 120
TEMPERATURE (C)
TEMPERATURE (C)
Figure 17. VBO
19.4 19.2 19.0 CURRENT (mA) 18.8 18.6 18.4 18.2 18.0 17.8 17.6 17.4 -40 -20 0 20 40 60 80 100 120 VOLTAGE (V) 17.0 16.8 16.6 16.4 16.2 16.0 15.8 -40
Figure 18. ENhyste
-20
0
20
40
60
80
100
120
TEMPERATURE (C)
TEMPERATURE (C)
Figure 19. IBO
Figure 20. VCC_clamp
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290 240 FREQUENCY (kHz) 190 140 90 40 0.2
0.3
0.4
0.5
0.6
0.7 Irt (mA)
0.8
0.9
1.0
1.1
1.2
Figure 21. Irt and Appropriate Frequency
APPLICATION INFORMATION The NCP1392 is primarily intended to drive low cost half bridge applications and especially resonant half bridge applications. The IC includes several features that help the designer to cope with resonant SPMS design. All features are described thereafter: * Wide Operating Frequency Range: The internal current controlled oscillator is capable to operate over wide frequency range up to 250 kHz. Minimum frequency accuracy is $3%. * Fixed Dead-Time: The internal dead-time helping to fight with cross conduction between the upper and lower power transistors. Three versions with different dead time values are available to cover wide range of applications. * 100 ms PFC Timer: Fixed delay is placed to IC operation whenever the driver restarts (VCCON or BO_OK detect events). This delay assures that the bulk voltage will be stabilized in the time the driver provides pulses on the outputs. Another benefit of this delay is that the soft start capacitor will be full discharged before any restart. * Brown-Out Detection: The BO input monitors bulk voltage level via resistor divider and thus assures that the application is working only for wanted bulk voltage band. The BO input sinks current of 18.2 mA until the VrefBO threshold is reached. Designer can thus adjust the bulk voltage hysteresis according to the application needs.
* Non-Latched Enable Input: The enable comparator
*
*
input is connected in parallel to the BO terminal to allow the designer stop the output drivers when needed. There is no PFC delay when enable input is released so skip mode for resonant SMPS applications and dimming for light ballast applications are possible. Internal VCC Clamp: The internal zener clamp offers a way to prepare passive voltage regulator to maintain VCC voltage at 16 V in case the controller is supplied from unregulated power supply or from bulk capacitor. Low Startup Current: This device features maximum startup current of 50 mA which allows the designer to use high value startup resistor for applications when driver is supplied from the auxiliary winding. Power dissipation of startup resistor is thus significantly reduced.
Current Controlled Oscillator
The current controlled oscillator features a high-speed circuitry allowing operation from 50 kHz up to 500 kHz. However, as a division by two internally creates the two Q and Q outputs, the final effective signal on output Mlower and Mupper switches between 25 kHz and 250 kHz. The VCO is configured in such a way that if the current that flows out from the Rt pin increases, the switching frequency also goes up. Figure 22 shows the architecture of this oscillator.
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NCP1392B
V DD
S D
Q
A
+ -
Rsoft-start R t Csoft-start Rt Delay
+ -
IDT Ct Vref Rt
+ -
Vref
+ -
CLK R Q B Dead Time
From PFC Delay PON Reset From EN Cmp.
Figure 22. The Internal Current Controlled Oscillator Architecture
The internal timing capacitor Ct is charged by current which is proportional to the current flowing out from the Rt pin. The discharging current IDT is applied when voltage on this capacitor reaches 2.5 V. The output drivers are disabled during discharge period so the dead time length is given by the discharge current sink capability. Discharge sink is disabled when voltage on the timing capacitor reaches zero and charging cycle starts again. The charging current and thus also whole oscillator is disabled during the PFC delay period to keep the IC consumption below 400 mA.
This is valuable for applications that are supplied from auxiliary winding and VCC capacitor is supposed to provide energy during PFC delay period. For the resonant applications and light ballast applications it is necessary to adjust minimum operating frequency with high accuracy. The designer also needs to limit maximum operating and startup frequency. All these parameters can be adjusted using few external components connected to the Rt pin as depicted in Figure 23.
NCP1392
Rt
V CC Rfmax Rfstart D1 Rt (to secondary voltage regulator) CSS TLV431 (to primary current sensor) Rcomp Ccomp Rfmax-OCP Rbias
Voltage Feedback
Current Feedback
Figure 23. Typical Rt Pin Connection
The minimum switching frequency is given by the Rt resistor value. This frequency is reached if there is no optocoupler or current feedback action and soft start period
has been already finished. The maximum switching frequency excursion is limited by the Rfmax selection. Note that the Fmax value is influenced by the optocoupler
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NCP1392B
saturation voltage value. Resistor Rfstart together with capacitor CSS prepares the soft start period after PFC timer elapses. The Rt pin is grounded via an internal switch during the PFC delay period to assure that the soft start capacitor will be fully discharged via Rfstart resistor. There is a possibility to connect other control loops (like current control loop) to the Rt pin. The only one limitation lies in the Rt pin reference voltage which is VrefRt = 3.5 V. Used regulator has to be capable to work with voltage lower than VrefRt. The TLV431 shunt regulator is used in the example from figure 4 to prepare current feedback loop. Diode D1 is used to enable regulator biasing via resistor Rbias. Total saturation voltage of this solution is 1.25 + 0.6 = 1.85 V for
Vbulk
room temperature. Shottky diode will further decrease saturation voltage. Rfmax - OCP resistor value, limits the maximum frequency that can be pushed by this regulation loop. This parameter is not temperature stable because of the D1 temperature drift.
Brown-Out Protection
The Brown-Out circuitry (BO) offers a way to protect the application from low DC input voltages. Below a given level, the controller blocks the output pulses, above it, it authorizes them. The internal circuitry, depicted by Figure 24, offers a way to observe the high-voltage (HV) rail.
Rupper
BO
+ -
Rlower SW IBO + - VrefBO
20ms Filter
BO_OK to and gates
To PFC Delay
Figure 24. The internal Brown-Out Configuration with an Offset Current Sink
High Level for 50 ms after VCC ON
A resistive divider made of Rupper and Rlower, brings a portion of the HV rail on Pin 3. Below the turn-on level, the 18.2 mA current sink (IBO) is on. Therefore, the turn-on level is higher than the level given by the division ratio brought by the resistive divider. To the contrary, when the
IBO is on Vref BO + V bulk1 @ IBO is off Vref BO + V bulk2 @ R lower R lower ) R upper
internal BO_OK signal is high (PFC timer runs or Mlower and Mupper pulse), the IBO sink is deactivated. As a result, it becomes possible to select the turn-on and turn-off levels via a few lines of algebra:
* I BO @
R lower @ R upper R lower ) R upper
(eq. 1)
R lower R lower ) R upper V bulk1 * V bulk2
(eq. 2)
We can extract Rlower from Equation 2 and plug it into Equation 1, then solve for Rupper:
R lower + Vref BO @
(eq. 3)
I BO @ V bulk2 * Vref BO V bulk2 * Vref BO Vref BO
(eq. 4)
R upper + R lower @
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If we decide to turn-on our converter for Vbulk1 equals 350 V and turn it off for Vbulk2 equals 250 V, then for IBO = 18.2 mA and VrefBO = 1.0 V we obtain: Rupper = 5.494 MW Rlower = 22.066 kW The bridge power dissipation is 4002 / 5.517 MW = 29 mW when front-end PFC stage delivers 400 V. Figure 25 simulation result confirms our calculations.
Figure 25. Simulation Results for 350/250 ON/OFF Brown-Out Levels
The IBO current sink is turned ON for 50 ms after any controller restart to let the BO input voltage stabilize (there can be connected big capacitor to the BO input and the IBO is only 18.2 mA so it will take some time to discharge). Once the 50 ms one shoot pulse ends the BO comparator is
supposed to either hold the IBO sink turned ON (if the bulk voltage level is not sufficient) or let it turned OFF (if the bulk voltage is higher than Vbulk1). See figures 10 - 13 for better understanding on how the BO input works.
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Figure 26. BO Input Functionality - Vbulk2 < Vbulk < Vbulk1
Figure 27. BO Input Functionality -Vbulk2 < Vbulk < Vbulk1, PFC Start Follows
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Figure 28. BO Input Functionality - Vbulk > Vbulk1
Figure 29. BO Input Functionality - Vbulk < Vbulk2, PFC Start Follows Non-Latched Enable Input
The non-latched input stops output drivers immediately the BO terminal voltage grows above 2 V threshold. The enable comparator features 100 mV hysteresis so the BO terminal has to go down below 1.9 V to recover IC operation.
This input offers other features to the NCP1392 like dimming function for lamp ballasts (Figure 30) or skip mode capability for resonant converters (Figures 31 and 33).
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NCP1392B
VCC Vbulk
R2 Q2
Rupper + -
- +
VrefEN
0.5ms Filter
to AND gates
R3
R4 BO
Rlower Ihyste
SW
+ -
+ -
VrefBO
20ms Filter
to AND gates
To PFC Delay
Rt D1 R1 Dimming Input Q1 Rfstart Rt High Level for 50 ms after VCC ON
NCP1392
CSS
GND
Figure 30. Dimming Feature Implementation Using Nonlatched Input on BO Terminal
The dimming feature can be easily aid to the ballast application by adding two bipolar transistors (Figure 14). Transistor Q2 pullup BO input when dimming signal is high.
In the same time the Q1 discharges soft start capacitor via diode D1. Ballast application is enabled (including soft-start phase) when dimming signal becomes low again.
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NCP1392B
Vbulk
Rupper + -
- +
VrefEN
0.5ms Filter
to AND gates
D1
BO
Rlower Ihyste
SW
+ -
+ -
VrefBO
20ms Filter
to AND gates
To PFC Delay
R2
Rt High Level for 50 ms after VCC ON Rfstart Voltage Feedback Rt NCP1392
R1
CSS
GND
Figure 31. Skip Mode Feature Implementation (Temperature Dependent, Cost Effective)
VCC
R1 Q1
R6
Vbulk
+ - Rupper R3 BO
- +
VrefEN
0.5ms Filter
to AND gates
R2
Rlower Soft-Start After Skip (If Needed) D1 Ihyste
SW
+ -
+ -
VrefBO
20ms Filter
to AND gates
To PFC Delay
R5
Rt High Level for 50 ms after VCC ON
C1 Q2 Voltage Feedback
Rfstart
Rt
NCP1392
R4
CSS
GND
Figure 32. Skip Mode with Transistor Feature Implementation (Temperature Dependent, Cost Effective)
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VCC Vbulk
R1 Q1
R6 Rupper + - R3 BO
- +
VrefEN
0.5ms Filter
to AND gates
R2
Rlower Ihyste
SW
+ -
+ -
VrefBO
20ms Filter
to AND gates
To PFC Delay
R5
Rt High Level for 50 ms after VCC ON
C1 Voltage Feedback IC1 TLV431 R4
Rfstart
Rt
NCP1392
CSS
GND
Figure 33. Skip Mode Feature Implementation (Better Accuracy)
Figures 31 and 33 shows skip mode feature implementation using NCP1392 driver. Voltage across resistor R1 (R4) increases when converter enters light load conditions. The enable comparator is triggered when voltage across R1 is higher than Vref EN + Vf(D1) for connection from Figure 31 (voltage across R4 is higher than 1.24 V for connection from figure 16). IC then prevents outputs from pulsing until BO terminal voltage decreases below 1.92 V.
Note that enable comparator serves also as an automatic overvoltage protection. When bulk voltage is too high, the enable input is triggered via BO divider.
The High-Voltage Driver
Figure 34 shows the internal architecture of the high-voltage section. The device incorporates an upper UVLO circuitry that makes sure enough Vgs is available for the upper side MOSFET. The VCC for floating driver section is provided by Cboot capacitor that is refilled by external bootstrap diode.
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NCP1392B
Boot Vbulk
Pulse Trigger
Level Shifter
S R
Q Q
Cboot Hgd
UV Detect
HB
DEAD TIME
Dboot from PFC Delay VCC Vaux +
B
B A Lgd
A
Delay
GND from latch high if OK
Figure 34. The Internal High-Voltage Section of the NCP1392
The A and B outputs are delivered by the internal logic, as depicted in block diagram. This logic is constructed in such a way that the Mlower driver starts to pulse firs after any driver restart. The bootstrap capacitor is thus charged during first pulse. A delay is inserted in the lower rail to ensure good
matching between these propagating signals. As stated in the maximum rating section, the floating portion can go up to 600 Vdc and makes the IC perfectly suitable for offline applications featuring a 400 V PFC front-end stage.
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NCP1392B
PACKAGE DIMENSIONS
SOIC-8 NB CASE 751-07 ISSUE AJ
-X- A
8 5
B
1
S
4
0.25 (0.010)
M
Y
M
-Y- G
K
NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSION A AND B DO NOT INCLUDE MOLD PROTRUSION. 4. MAXIMUM MOLD PROTRUSION 0.15 (0.006) PER SIDE. 5. DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.127 (0.005) TOTAL IN EXCESS OF THE D DIMENSION AT MAXIMUM MATERIAL CONDITION. 6. 751-01 THRU 751-06 ARE OBSOLETE. NEW STANDARD IS 751-07. DIM A B C D G H J K M N S MILLIMETERS MIN MAX 4.80 5.00 3.80 4.00 1.35 1.75 0.33 0.51 1.27 BSC 0.10 0.25 0.19 0.25 0.40 1.27 0_ 8_ 0.25 0.50 5.80 6.20 INCHES MIN MAX 0.189 0.197 0.150 0.157 0.053 0.069 0.013 0.020 0.050 BSC 0.004 0.010 0.007 0.010 0.016 0.050 0_ 8_ 0.010 0.020 0.228 0.244
C -Z- H D 0.25 (0.010)
M SEATING PLANE
N
X 45 _
0.10 (0.004)
M
J
ZY
S
X
S
SOLDERING FOOTPRINT*
1.52 0.060
7.0 0.275
4.0 0.155
0.6 0.024
1.270 0.050
SCALE 6:1 mm inches
*For additional information on our Pb-Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D.
The products described herein (NCP1392/D), may be covered by one or more of the following U.S. patents; 6,097, 075; 7176723; 6,362, 067. There may be other patents pending.
ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. "Typical" parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including "Typicals" must be validated for each customer application by customer's technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner.
PUBLICATION ORDERING INFORMATION
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